1. Field of the Invention
The present invention relates to the field of digital computer systems and, more particularly, to the field of memory systems used in digital computer systems.
2. Description of the Related Art
Modern microprocessors use a broad range of memory systems for processing and storage of data. Over the years, technical advances have significantly increased the capacity of digital memories and also the speed with which the memories can transfer data. In current digital processing systems, various types of semiconductor memories are used. One of the most common types of semiconductor memory is random access memory (RAM). While the various types of semiconductor memories are available in different design formats, the structure, organization and access of information in these memory structures is essentially the same. In random access memory, information can be stored in a flip-flop type circuit, or simply as a charge on capacitors.
RAM is generally organized within the system into addressable blocks, each containing a predetermined number of memory cells. Each memory cell within a RAM represents a bit of information. The memory cells are organized into rows and columns. Each row of memory cells forms a word. Each memory cell within a row is coupled to the same wordline which is used to activate the memory cells within the row. The memory cells within each column of a block of memory are coupled to a pair of bitlines which are used to read data from the activated memory cell or write data to the activated memory cell. The pair of bitlines includes a bitline and an inverse (complement) bitline. A memory cell is therefore accessed by activating the appropriate wordline and pair of bitlines.
Generally, before a memory access operation is performed to or from a memory cell within a block of memory, the pairs of bitlines within that block of memory are all precharged to a specified voltage level. A memory access operation includes both write and read operations. The precharge operation equalizes the voltage level of the bitlines at a known level, to enhance reliability of the data written to a cell and to allow quick detection of data read from a cell. Memory bitlines are typically precharged to equilibrate the dual ended, true/complement differential bitline wires. This method allows a low level (typically 100 mv) signal to be developed with a small memory cell into a large capacitive load bitline. The control signals activating and deactivating the precharge must be margined into the offstate before the wordline turns on and the memory call can drive the bitline. As device feature sizes and voltage levels decrease, this margin is increasingly difficult to obtain while maintaining maximum performance (max frequency minimum clk cycle time) operation.